Progress in voltage and current mode on-chip analog-to-digital converters for CMOS image sensors

Two 8 bit successive approximation analog-to-digital converter (ADC) designs and a 12 bit current mode incremental sigma delta (Z-L) ADC have been designed, fabricated, and tested. The successive approximation test chip designs are compatible with active pixel sensor (APS) column parallel architectures with a 20.4 j.tm pitch in a 1.2 m n-well CMOS process and a 40 tm pitch in a 2 j.tm n-well CMOS process. The successive approximation designs consume as little as 49 j.tW at a 500 KHz conversion rate meeting the low power requirements inherent in column parallel architectures. The current mode incremental :-ADC test chip is designed to be multiplexed among 8 columns in a semi-column parallel current mode APS architecture. The higher accuracy ADC consumes 800 tW at a 5 KHz conversion rate.